1. Field of the Invention
This invention relates to a 3-D semiconductor Non-Volatile Memory (NVM) cell devices. The semiconductor NVM cell device of the invention can be processed with the advanced finFET (fin-shape Field Effect Transistor) process technology applied for manufacturing standard Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOSFET) below 20 nm process technology nodes. In particular, the 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device of the invention consists of one floating metal gate for storing charges and two semiconductor fins for the body of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and control gate, respectively.
2. Description of the Related Art
CMOS process becomes the most popular fabrication process for Application Specific Integrated Circuit (ASIC). An ASIC contains the specific functionality of a device or a system on a single Integrated Circuit (IC) or a chip. In digital age the entire electronic devices or equipments are controlled and operated by IC chips. For various applications the capability of implementing multiple functions on the same circuit hardware becomes economically desirable. Thus, the flexibility to change for the specific functionality or configuration operating on IC chips is required for many various applications. For instance, the initial programming and configuring a microprocessor require a programmable non-volatile memory to store the programmed instructions. The non-volatile memory retains its stored digital information, even when the powers for the electronic systems are “off”. The stored digital information or instructions can be recalled, when the electronic system are turned on. Furthermore, the programmable instructions shall be allowed to change any time without changing the hardware during developments. The non-volatile memory of storing programmed codes and data for electronic systems are done by Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. EEPROM is a semiconductor NVM capable of being erased and programmed by applying electrical voltage biases to the electrodes of memory devices.
In the conventional EEPROM fabrication process, the control gates of EEPROM memory cells are fabricated above an isolated conductive layer as the floating gate or a stack of dielectric layers like Oxide-Nitride-Oxide (ONO) for storing electrical charges on top of silicon channel surfaces. However, in the conventional CMOS process broadly applied to most ASIC fabrications, only one single conducting gate layer is fabricated for the switching gates of MOSFET devices. The EEPROM fabrication process for the extra charge storing layers requires several process steps such as film deposition, etching, and photolithography for patterning. These additional process steps in comparison with the conventional CMOS process result in fabrication cost increases, process complexity, circuit yield impact, and longer process time. Thus, EEPROM processed with no extra storage layer and compatible with CMOS baseline process are very desirable for embedded EEPROM ASICs.
Meanwhile, on the road of scaling down MOSFET devices to gain the higher device density and higher performance in IC, the conventional planar structures of MOSFET devices illustrated in FIG. 1a have reached a limit below 20 nm process technology node. The deteriorated short channel margin for planar MOSFET becomes the major hurdle for scaling down the MOSFET devices. To overcome such hurdle, 3-D finFET devices illustrated in FIG. 1b have been becoming the main stream MOSFET devices below 20 nm process technology nodes. To meet the need for embedded non-volatile memory storage below 20 nm process technology nodes in CMOS, we have proposed a new semiconductor non-volatile memory device based on the 3-D finFET process technology. The Single Floating Gate Non-Volatile Memory (SFGNVM) devices of the invention are single gate devices and fully compatible with the 3-D finFET process without involving any new process or any unconventional material in the process technology.
In another aspect of scaling down semiconductor non-volatile device beyond 20 nm process technology node, the conventional semiconductor non-volatile memory devices are also hitting a hurdle for floating gate non-volatile memory devices due to the limitation of lithographic and etch processes such as double-gate alignment and ultra-high an-isotropic etch aspect ratio in the stacked double-gate process. Since the SFGNVM devices of the invention are single-gate devices the limitation of process capability for the stacked double-gate in 20 nm and beyond is automatically lifted off.